Integrated circuits are formed on semiconductor wafers. The semiconductor wafers are then sawed into chips. The formation of integrated circuits includes many process steps such as deposition, chemical mechanical polish (CMP), plating, and the like. Accordingly, wafers are transported between different equipments.
A challenge faced by integrated circuit manufacturing industry is that to improve cost efficiency, wafers become increasingly larger. In the meantime, wafers also become increasingly thinner. Therefore, the thin wafers suffer from breakage, particularly during the transportation and the CMP process, during which mechanical stress may be applied to the wafers.
To reduce the likelihood of breakage, thin wafers may need to be strengthened. In conventional processes, in order to perform wafer thinning, a carrier is bonded to the wafers first, and then the wafer is thinned, for example, through a backside grinding step. The bonding between the carrier and the wafer is performed through an adhesive. After the wafer thinning process, additional process steps may be performed on the wafer. The additional process steps may include dry etches, physical vapor depositions (PVDs), plasma enhanced chemical vapor depositions (PECVDs), which process steps involve the use of plasma. The plasma interacts with the exposed portions of the adhesive, and may cause bubbles to be generated in the adhesive. The generated bubbles may apply upward forces to the wafer, and the upward forces may not be uniformly applied to different parts of the respective wafer. Accordingly, in subsequent process steps, the total wafer thickness variation (TTV) of the wafer is adversely affected. Further, the bubbles may cause some portions of the adhesive to be pushed to a level higher than the top surface of the wafer, and the subsequent manufacturing processes are affected.